1. Field of the Invention
The present invention relates to a data processing apparatus, a memory controller and an access control method of the memory controller, and in particular to a data processing apparatus provided with an operation circuit and a memory which receives access from the operation circuit, wherein the memory stores write data outputted from the operation circuit and an error correcting code corresponding to the write data in association with each other.
2. Description of Related Art
A data processing apparatus has an operation circuit (for example, a Central Processing Unit: CPU) and a memory which is accessed by the CPU. The CPU executes various processings by accessing the memory. In recent semiconductor devices, miniaturization of semiconductor elements has progressed, and the capacity of the memory has increased. However, as the capacity of the memory increases, the rate of occurrence of element defects during the manufacturing process or during the duration of use increases. If a defective element occurs in the memory, then it is not possible to hold accurate data. There is a problem that, when the CPU operates on the basis of such inaccurate data, a malfunction occurs in the data processing apparatus.
Therefore, an error correcting code (ECC) is added to data to be stored into the memory, and the error correcting code is read from the memory together with the data to perform error correction of the data. By performing such error correction, it is possible to, even if the memory includes a certain number of element defects, treat the memory similarly to a memory without an element defect.
The CPU and the memory are generally connected via a data bus having a predetermined bus width. The CPU transmits and receives data with a data width within the range of the bus width, to and from the memory. For example, if the bus width is 32 bits, the maximum data width of data which the CPU can transmit and receive to and from the memory is 32 bits (hereinafter, the data width of 32 bits is referred to as “1 word”). However, the CPU does not necessarily perform transmission and receiving of data with the memory on a word basis. Indeed, it may perform transmission and receiving of data with the memory on a half word (data whose data width is 16 bits) basis or on a byte (data whose data width is 8 bits) basis according to a program to be executed.
In order to perform error correction using an error correcting code in such a data processing apparatus, the error correcting code is generated for each of the minimum unit of data transmitted and received. However, when the error correcting code is generated for the minimum unit of data, there is a problem that, since the percentage of occupation of the memory storage capacity by error correcting codes increases, the memory storage capacity cannot be effectively used. For example, the error correcting code for 8-bit data has a data width of 5 bits. In this case, about 40% of the memory storage capacity is used for the error correcting codes. In comparison, if the error correcting code is generated for each 1 word, then the data width of the error correcting code is 7 bits. That is, the amount of data can be suppressed more by generating the error correcting code for a larger unit of data.
Accordingly, JP-A-HEI-11-194975 discloses a memory system 100 which generates the error correcting code for each 1 word irrespective of the data width of data transmitted and received between the CPU and the memory. FIG. 7 shows the block diagram of the memory system 100. As shown in FIG. 7, the memory system 100 has a memory 101, a CPU 102, a writing control circuit 110, a reading control circuit 111, a readout necessity judgment circuit 112 and an error correction circuit 132. The error correction circuit 132 has bus control circuits 104a and 104b, a latch circuit 105, a partial write control circuit 106, selectors 107a to 107d, a correcting code generation circuit 108, and an error detection-correction circuit 109. In the memory system 100, the CPU 102 and the memory 101 are connected via a bus with a data width of 32 bits. That is, the CPU 102 and the memory 101 assume 32 bits as 1 word.
FIG. 8 shows a timing chart showing the operation of the memory system 100 in the case where the memory system 100 writes data having a data width of 8 bits or 16 bits into the memory. As shown in FIG. 8, in the case of writing 8 bits or 16 bits, the readout necessity judgment circuit 112 instructs the reading control circuit 111 to output a reading signal OE-N on the basis of a data size signal first. On the basis of this reading signal OE-N, data to be stored is outputted from the memory 101. After that, a writing signal WE-N is outputted from the writing control circuit 110. Then, input data is written into the memory 101. That is, the memory system 100 reads data Dr and an error correcting code ECC from the memory 101 by the first reading operation, and generates data Dr′ by the error detection-correction circuit 109. Then, by the next writing operation, the memory system 100 generates input data DW to be inputted into the memory 101 with data Dp (write data outputted from the CPU 102) to be inputted into a selector which has been selected by the partial write control circuit 106 and the data Dr′ to be inputted into a selector which has not been selected by the partial write control circuit 106. Then, an error correcting code ECC is generated for this input data DW. After that, both of this error correcting code ECC and the input data DW are written into the memory 101.
On the other hand, FIG. 9 shows a timing chart showing the operation of the memory system 100 in the case of writing 1-word data into the memory 101. In the case of writing data with 1 word, the readout necessity judgment circuit 112 instructs the reading control circuit 111 not to output a reading signal OE-N. Then, when data Dp outputted from the CPU 102 reaches the bus control circuit 104a, the writing control circuit 110 outputs a writing signal WE-N. After that, the data Dp is written into the memory 101 as input data to the memory 101.
In the memory system 100, when the 1-word data is written, the data Dp outputted by the CPU 102 is written, without reading data from the memory 101 in advance. Thereby, the memory system 100 reduces access time required when the 1-word data is written.